1. Field of the Invention
The present invention relates to an apparatus for testing a semiconductor integrated circuit. More particularly the present invention relates to an apparatus for testing a semiconductor integrated circuit including an analog-to-digital converter circuit for converting an analog signal into a digital signal or a digital-to-analog converter circuit for converting a digital signal into an analog signal, as well as to a method of testing a semiconductor integrated circuit using the apparatus.
2. Background Art
An apparatus for testing a semiconductor integrated circuit is called a tester. Recently, in relation to a system LSI embodied in a one-chip semiconductor integrated circuit (a one-chip LSI) consisting of a plurality of functionally-systematized circuit modules or embodied in a hybrid integrated circuit (a chip set LSI), combination of high-performance and precision digital and analog circuits (i.e., a system LSI handling a mixed signal) has been rapidly pursued. Even in relation to a test apparatus for use with a semiconductor integrated circuit, development of a test apparatus capable of handling a mixed signal is also pursued. Tester manufacturers have provided testers compatible with a semiconductor integrated circuit using a mixed signal.
A tester compatible with a semiconductor integrated circuit using a mixed signal has a tendency to become expensive in the course of ensuring compliance with high performance specifications. For this reason, moves are afoot to recycle an existing low-speed, low-precision tester which has been used for, e.g., a logic LSI, to thereby avoid a hike in the price of a tester.
A big problem with such a test apparatus lies in a test for a digital-to-analog converter circuit (DAC) for converting a digital signal into an analog signal as well as in a test for an analog-to-digital converter circuit (ADC) for converting an analog signal into a digital signal. In association with an increase in the precision of the characteristic test, embodiment of a low-cost test apparatus compatible with a semiconductor integrated circuit including the DAC and ADC has posed a challenge.
In a testing environment of a general tester, a plurality of DUT (device under test) circuit boards (simply called “DUT boards”) and connection jigs for connecting a tester with a DUT, such as cables, are provided at a plurality of points along a measurement path extending from measurement equipment in the tester to DUT. The measurement path is long and accounts for occurrence of noise and a drop in measurement accuracy. Further, simultaneous testing of a plurality of DUTs is also difficult. A limitation is imposed on the speed of a low-speed tester, and hence the low-speed tester cannot conduct a test at a real operating speed, thereby posing a fear of an increase in a time required for conducting mass-production testing of a system LSI.
Japanese Patent Application Laid-Open No. 316024/1989 describes a tester. The tester is equipped with a memory device for storing conversion data at an address designated by input data which have entered into a DAC of a test circuit. An analog signal which has been subjected to digital-to-analog conversion is input to an ADC, and an output from the ADC is sequentially stored in the memory device. After conversion of all the input data sets has been completed, the conversion data stored in the memory device are sequentially delivered to a tester. The tester sequentially compares the input data with the conversion data, thus producing a test conclusion.
However, the tester must supply data to be input to the DAC, an address to be used for storing conversion data into a memory device, and a control signal. Moreover, data stored in the memory device must be supplied to the tester. Further, there is the probability that noise arising in a long measurement path extending from the tester to a DUT may deteriorate precision of measurement. Further, the majority of pin electronics provided on the tester are occupied for testing a single DUT, thereby posing a difficulty in simultaneous measurement of a plurality of DUTs. Further, communication for transmitting conversion data to the tester is time consuming, and test conclusions are produced after completion of all tests. Hence, shortening of a test time is also difficult.